ATMEGA169P-16MCHR【PDF 87/274 页】MCU AVR 16KB FLASH 16MHZ 64-VQFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3753

83页 84页 85页 86页 [87页]88页 89页 90页 91页

2005 Microchip Technology Inc.

Preliminary

DS41265A-page 175

PIC16F946

14.11 SSP I2C Operation

The SSP module in I2C mode, fully implements all

slave functions, except general call support, and pro-

vides interrupts on Start and Stop bits in hardware to

facilitate firmware implementations of the master func-

tions. The SSP module implements the Standard mode

specifications, as well as 7-bit and 10-bit addressing.

Two pins are used for data transfer. These are the

RC6/TX/CK/SCK/SCL/SEG9 pin, which is the clock

(SCL), and the RC7/RX/DT/SDI/SDA/SEG8 pin, which

is the data (SDA).

The SSP module functions are enabled by setting SSP

enable bit SSPEN (SSPCON<5>).

FIGURE 14-7:

SSP BLOCK DIAGRAM

(I2C MODE)

The SSP module has five registers for the I2C operation,

which are listed below.

SSP Control Register (SSPCON)

SSP Status Register (SSPSTAT)

Serial Receive/Transmit Buffer (SSPBUF)

SSP Shift Register (SSPSR) – Not directly

accessible

SSP Address Register (SSPADD)

The SSPCON register allows control of the I2C

operation. Four mode selection bits (SSPCON<3:0>)

allow one of the following I2C modes to be selected:

I2C Slave mode (7-bit address)

I2C Slave mode (10-bit address)

I2C Slave mode (7-bit address), with Start and

Stop bit interrupts enabled to support Firmware

Master mode

I2C Slave mode (10-bit address), with Start and

Stop bit interrupts enabled to support Firmware

Master mode

I2C Start and Stop bit interrupts enabled to

support Firmware Master mode; Slave is idle

Selection of any I2C mode with the SSPEN bit set

forces the SCL and SDA pins to be open drain, pro-

vided these pins are programmed to inputs by setting

the appropriate TRISC bits. Pull-up resistors must be

provided externally to the SCL and SDA pins for proper

operation of the I2C module.

Additional information on SSP I2C operation can be

found in the “PICmicro Mid-Range MCU Family

Reference Manual” (DS33023).

14.12 Slave Mode

In Slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISC<7:6> set). The SSP module will

override the input state with the output data when

required (slave-transmitter).

When an address is matched, or the data transfer after

an address match is received, the hardware automati-

cally will generate the Acknowledge (ACK) pulse, and

then load the SSPBUF register with the received value

currently in the SSPSR register.

There are certain conditions that will cause the SSP

module not to give this ACK pulse. They include (either

or both):

The Buffer Full bit BF (SSPSTAT<0>) was set

before the transfer was received.

The overflow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

In this case, the SSPSR register value is not loaded into

the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 14-3

shows the results of when a data transfer byte is received,

given the status of bits BF and SSPOV. The shaded cells

show the condition where user software did not properly

clear the overflow condition. Flag bit BF is cleared by

reading the SSPBUF register, while bit SSPOV is cleared

through software.

The SCL clock input must have a minimum high and low

for proper operation. For high and low times of the I2C

specification, as well as the requirements of the SSP

module, see Section 19.0 “Electrical Specifications”.

Read

Write

SSPSR reg

Match Detect

SSPADD reg

Start and

Stop bit Detect

SSPBUF reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT reg)

RC6/TX/

RC7/

Shift

Clock

MSb

RX/DT/

LSb

SDI/

CK/SCK/

SCL/SEG9

SDA/

SEG8

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式